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Contents. Tool Introduction QuestaSim is part of the and is the latest tool in Mentor Graphics tool suite for Functional Verification. The tool provides simulation support for latest standards of, 2001 standard and.
This tool is an advancement over Modelsim in its support for advanced Verification features like coverage databases, coverage driven verification, working with assertions, SystemVerilog constrained-random functionality. The aim of this tutorial is to understand the basics of working with SystemVerilog in the Questa tool environment.
This is going to be done using the example of a modified DLX execution block with a 2-stage pipeline. Establishing the Design Environment for compilation.
One time setup for a given directory used for simulation: Each time you create a directory for simulations you would have to do the following prompt% add questasim63 OR prompt% add modelsim. Copy the file that comes with this tutorial into the directory. This file sets up the necessary defaults for the Questa tool.
Create the library into which all the design units will be compiled. Do this by performing prompt% vlib mtilib (Note that the name “mtilib” corresponds to the variable “work” within the modelsim.ini file and is the library to which all the source code would be compiled to create a design single entity). Note that in some cases, if the compilation seems to crash for a reason you think is incorrect, it would be advisable to delete the “mtilib” directory (Use: rm –rf mtilib OR vdel –all) and re-create it as shown above. Setup for simulations within a directory for a given session: We assume the previous step has already been followed. Let us assume a directory has been setup up correctly and you come into this directory for a future simulation. You would still need to run the following commands each time you start a set of simulations for a given design within a directory. set paths to the Modelsim tool: prompt% add questasim63 OR prompt% add modelsim.
set environment variable MODELSIM to modelsim.ini prompt% setenv MODELSIM modelsim.ini At this point, all the path settings are good to go for the executables associated with Questa. It is assumed here that user is aware of the requirements for remote access from a Windows platform.
If not, the information can be obtained from the. Compilation and Simulation The Questa tool enables compilation of multiple design/verification/modeling units (each of which might be in a different language) into a common library (called the working library) and a common design representation. This enables each individual unit of the entire simulation to be compiled independantly and incremental compilation to be performed. At this point it must be stated that the compilation of the source code can either be done within the simulation environment (GUI) or on the command prompt. The simulation though MUST be performed within the simulation environment. In the interest of simplicity, we shall be performing the compilation of the source code on the command prompt of the UNIX/Linux terminal and providing a basic understanding of the tool capabilities. The other options and some helpful information will be touched upon in the section.
All the work should be done within the same folder say /Simulation/ To begin the compilation and simulation process, please download the following into a directory of your choice (/Simulation/). The Protected and unprotected Verilog RTL for the Design Under Test (DUT):. This corresponds to a watered down version of the DLX Execute Engine.
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In this case, we are only going to be looking at the arithmetic, shifting and memory based operations for the Execute Unit. A quick design specification for the Execute unit can be found at Design Spec:.
The SystemVerilog (SV) Testbench for this RTL:. the creation and use an to the DUT with a and a. the creation of a program which provides constrained stimulus to the DUT. This code has been written to provide the user a very basic introduction to a typical program structure with tasks and passing of signals into the DUT. the creation of a top level integration of the DUT, the interface and the program for sending stimulus to the design.
For this tutorial the testbench is only going to be used for the creation of constrained stimulus and for sending these stimuli into the DUT. The code provides an example for a standardized testing environment with At this point we can either do step3 in the GUI environment or at the command prompt.
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We shall continue with the command prompt. The next steps need to be performed each time a code change is performed and the changes need to be reflected in the simulations. Step1: Compilation of source code. Compile the Verilog RTL Model: A good feature is that Verilog(protected an unprotected) source files can be compiled out of order. Thus, we begin by compiling the protected verilog files by doing: prompt% vlog.vp Which results in the message: - Compiling module ALU - Compiling module ArithALU - Compiling module ExPreproc - Compiling module ShiftALU Top level modules: ALU ExPreproc Which implies that the high level modules in the hierarchy that were discovered are ALU and ExPreproc. We also need to compile the unprotected files which is done by performing the following on the command prompt: prompt% vlog.v This results in the following message: - Compiling module Top Top level modules: Top Which is on expected lines.
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Compile the SystemVerilog Testbench: The SV code shares the same ability to be compiled in any order. This holds as long as the includes from one file do not beat on those in another file. It is always suggested to follow an ordered compilation.
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